While conventional CMOS (Complementary Metal Oxide Semiconductor) integrated circuit processes may be used to create circuits which consume less power and occupy less space on a semiconductor substrate than similar circuits designed around a bipolar transistor fabrication process, bipolar devices, among other advantages, have the inherent ability to operate at higher speeds, drive larger capacitive loads, and switch faster than their MOS (Metal Oxide Semiconductor) counterparts. In an attempt to capture the advantages of both bipolar and MOS devices in one circuit, a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process has been developed.
In a BiCMOS process, bipolar and MOS transistors are both created on a single semiconductor substrate so that a portion of the resulting circuit operates using bipolar transistors while another portion of the same circuit operates using MOS transistors. As a result, one is given the freedom to design and implement a BiCMOS circuit which, among other advantages, consumes very lit fie power, occupies very little space, operates at very high speeds, and can drive large capacitive loads. A circuit such as this would have extensive applications in, for instance, battery-powered notebook computers where power consumption must be minimized in order to prolong battery life, size must be minimized to enhance portability, and processing speeds must be fast enough to handle advanced computational applications.
A logic gate is a circuit which executes a logical function on the logical values applied to the gate's input or inputs to produce an output and may exist within a main processing unit of a computer system or any of its peripherals. A logic gate may be configured to execute, for instance, NAND, NOR, AND, OR, XOR, inverter, etc. functions. Input data is gathered from, for instance, a cache or other buffer memory location, RAM, ROM, a latch or any register by processing circuitry which may contain the logic circuitry itself. After the data is transported to the logic gate, the logical function is applied to the input data in order to generate an output.
For demonstration purposes below, we will assume that a low voltage is that voltage which corresponds most closely with one particular logical state while a high voltage is that voltage which corresponds most closely with the opposite logical state. For example, in a 5 volt CMOS system, a voltage greater than approximately 2.5 V may be considered a logical "1", and a voltage less than approximately 2.5 V may be considered a logical "0". Of course, this correspondence may be reversed such that a low voltage represents a logical "1" and a high voltage represents a logical "0". In an alternate system which operates with a 3V supply, for example, a voltage greater than approximately 1.5 V may be considered a logical "1, and a voltage less than approximately 1.5 V may be considered a logical "0". Of course, this correspondence may again be reversed. In general, the lower voltage plus one-half the difference between the upper voltage minus the lower voltage of any system may be considered the approximate boundary between high and low voltages or alternate logical states for demonstration purposes herein.
In the circuit of FIG. 1, the gates of p-channel transistors 10 and 11 are coupled to inputs A and B respectively. The gates of n-channel transistors 13 and 16 are also coupled to input A while the gates of n-channel transistors 12 and 15 are coupled to input B. Transistors 10 and 11 are coupled to the supply voltage Vdd at one end and the base of npn bipolar transistor 14 at the other through base line 17. The collector of transistor 14 is coupled to the supply voltage Vdd while its emitter is coupled to the output of the circuit. The output of the circuit is isolated from Vss (usually a low voltage such as ground or 0 V) by transistors 15 and 16 in series, while the base of transistor 14 is isolated from Vss by transistors 12 and 13 in series.
FIG. 1 illustrates a circuit diagram for a prior an NAND gate logic circuit. This particular NAND gate accepts two inputs, A and B and generates, at its output, the result of the logical function A NAND B. Each input controls the operation of three transistors. Transistors 10 and 11 are p-channel transistors, so in order for the supply voltage Vdd to be applied to the base of transistor 14, thereby pulling the output high, either of inputs A or B must be at a low voltage. On the other hand, if both of the inputs A and B are at a high voltage, supply voltage Vdd will not be able to reach the base of transistor 14 through either of transistors 10 or 11, and all n-channel transistors 12, 13, 15, and 16 will be on thereby pulling the base of transistor 14 low (turning it off) and the output node low.
There are several problems with this type of a logic circuit. For example, note that the base of transistor 14 is coupled to the large MOS transistors 10, 11 and 12 through base line 17. In this type of configuration, the capacitive load on the base line 17 is greatly increased by the presence of parasitic capacitance within the large MOS transistors 10, 11 and 12. The more capacitance which appears on base line 17, the slower the device switching speed of pulling the base of transistor 14 high, which slows the ultimate switching speed of the entire circuit of FIG. 1 for pulling the output high. In fact, too much capacitance on base line 17 will make the circuit too slow to be practical. The larger the MOS transistors on base line 17, the more capacitance that the MOS transistor will contribute to base line 17. Likewise, the more MOS transistors appearing on base line 17, the greater the contribution to the capacitance on base line 17.
Another problem with the logic circuit of FIG. 1 is that the output node is pulled down by transistors 15 and 16 in series, and the base line 17, coupled to the base node of transistor 14, is pulled down by transistors 12 and 13 in series. It can take a long time for a series connection of MOS transistors to charge or discharge a node. The more MOS transistors appearing in series between the node to be pulled down (discharged) and Vss, the slower the device switching speed of pulling down that node. Likewise, the more MOS transistors appearing in series between the node to be pulled up (charged) and Vdd, the slower the device switching speed of pulling up that node.
If one were to expand the circuit of FIG. 1 from a two input NAND gate to, for instance, a four input NAND gate, two additional p-channel transistors would appear in parallel with transistors 10 and 11 between Vdd and base line 17, two additional n-channel transistors would appear in series with transistors 12 and 13 between base line 17 and Vss, and two additional n-channel transistors would appear in series with transistors 15 and 16 between the output node and Vss. Therefore, as the circuit of FIG. 1 expands to accept more inputs, the number of MOS transistors appearing in parallel on base line 17 increases proportionately. As discussed above, these additional large MOS transistors add capacitive loads to the base line, slowing down the circuit's switching speed. Also, the number of MOS transistors appearing in series to pull down base line 17 and the output node increases proportionately with additional inputs thereby also slowing down the circuit's switching speed. There comes a point where too many inputs incorporated into the circuit of FIG. 1 will make the device too slow to be practical. This is known as the fan-in limit and is typically about four inputs for a circuit like the one depicted in FIG. 1.
In the circuit of FIG. 2, the emitter of npn bipolar transistor 31 is coupled to the supply voltage Vdd while its base is receptive of input voltage A and its collector is coupled to output line 34. Note that in practice, bipolar transistors are generally not employed as input buffers to a circuit, as in FIG. 2, because the input resistance of a bipolar transistor is much lower than that of an MOS transistor. This is done here to better demonstrate a particular deficiency in the prior art. High input resistance is usually a desirable quality of a circuit. Transistors 30, 32, and 33 are n-channel MOS transistors. The gates of transistors 32 and 33 are coupled to input nodes B and C respectively. The drains of transistors 32 and 33 are coupled to Vdd while the sources of transistors 32 and 33 are coupled to the output line 34. The gate of precharge transistor 30 is coupled to the precharge node PRCH while its drain is coupled to the output line 34 and its source is coupled to Vss.
Consider the operation of the dynamic circuit of FIG. 2. To clarify why this circuit is classified as a dynamic circuit we must analyze its operation over time. First, a circuit such as this must be reset or precharged. To do this, a low voltage is applied to the control terminals A, B, and C of transistors 31, 32, and 33 respectively. A high voltage is applied to the gate of transistor 30 at the PRCH node. In doing so, the output line 34 is drained of charge until it reaches a low voltage approximately equal to Vss. Then transistor 30 is turned off by applying a low voltage to the PRCH gate terminal of transistor 30. At this point, the circuit is ready to be triggered.
The circuit executes a logical OR function whereby when the voltage at any of the terminals A, B, or C of transistors 31, 32, or 33, respectively, switches to a high voltage, the output line 34 will also switch to a high voltage. In other words, any change in the logical state of terminals A, B, or C of transistors 31, 32, or 33, respectively, will cause the output line 34 to switch logical states. For instance, assume the base terminal A of transistor 31 goes high. This will turn on the bipolar transistor 31 thereby pulling the output line 34 high. The bipolar transistor 31 will then drive the output line 34 and cause it to remain high until the circuit is again reset as described above.
The circuit of FIG. 2 suffers from several problems. For example, one problem relates to MOS capacitance loading on its output line 34 in a similar manner in which the circuit of FIG. 1 suffers from MOS capacitance loading on its base line 17. The capacitance from large MOS transistors 30, 32 and 33 will load the output line with capacitance thereby significantly slowing the speed of this circuit. Note that additional inputs to the circuit of FIG. 2 would require that additional MOS transistors be attached in parallel between the supply voltage Vdd and the output line 34. Therefore, each additional input to the circuit of FIG. 2 will add a proportionate amount of MOS capacitance to the output line 34, slowing the switching speed of the circuit until the circuit becomes too slow to be practical.
Now let us assume the circuit of FIG. 2 is reset, and this time, node B on the gate of MOS transistor 32 goes high thereby pulling the output line 34 high. The MOS transistor 32 will now drive the output line 34 until the circuit is again reset as described above. In this case, bipolar transistor 31 will have a low base voltage at base node A and a high emitter voltage attached to the output line 34. This condition is known as negative or reverse bias across the pn base-emitter junction of bipolar transistor 31. Such a condition is a reliability problem. Reverse biasing a base-emitter junction causes hot electron injection in the transistor. This can result in the creation of base-emitter leakage current and a drop in transistor gain which is a function of the base-emitter reverse bias stress voltage and stress time. This leakage current and drop in transistor gain degrades the performance of the bipolar transistor thereby degrading the performance of the entire circuit. Thus, the reliability of the microprocessor in which the circuit operates, and indeed the reliability of the entire computer system in which such a microprocessor resides, is jeopardized by such reverse biasing of the base-emitter junction of the bipolar transistor.
Transistors 30 and 33 will not experience such reliability problems because they are MOS transistors. However, any npn bipolar transistor whose emitter is coupled to the output line 34, such as transistor 31, will suffer the reverse bias base-emitter junction reliability concern discussed above. On the other hand, any large MOS transistor coupled to the output line 34, such as transistors 30, 32, and 33, while not experiencing such reliability problems, will load the output line 34 with capacitance thereby slowing the speed of the circuit.
Therefore, to increase device speed it is desirable to use bipolar transistors to drive circuit output lines since bipolar transistors can deliver much more current to the output line per unit of capacitive load than can MOS transistors. The more current delivered to the output of a circuit, the better able that circuit is of driving large capacitive loads. It is impractical to drive large capacitive loads quickly with MOS transistors because they themselves contribute too much capacitance to an output line without providing much current in return. But if bipolar transistors are used on a circuit output line, some type of method must be employed to protect the bipolar transistors on the output line from either receiving too much reverse bias base-emitter voltage stress or reducing the amount of time a reverse bias base-emitter voltage is present.